The memory system includes: a first sub-buffer for storing an address map table; a second sub-buffer configured to sequentially store logical addresses, and store a latest received logical address in a specific region; a third sub-buffer including write buffers configured to store a size of data corresponding to each of the logical addresses; a storage device comprising memory blocks; a processor configured to control the storage device to store the data in memory blocks corresponding to the logical addresses using a SLC method; and an address manager configured to select at least two logical addresses comprising the latest received logical address. The processor is configured to control the storage device to store data read from memory blocks corresponding to the at least two logical addresses in a memory block using an MLC method. The address manager is configured to release a write buffer corresponding to the latest received logical address.