Invention Grant
- Patent Title: Testing of lockstep architecture in system-on-chips
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Application No.: US17301927Application Date: 2021-04-19
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Publication No.: US11550684B2Publication Date: 2023-01-10
- Inventor: Neha Srivastava , Krishan Bansal
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G06F11/30 ; G06F11/263 ; G06F9/52

Abstract:
A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.
Public/Granted literature
- US20220334936A1 TESTING OF LOCKSTEP ARCHITECTURE IN SYSTEM-ON-CHIPS Public/Granted day:2022-10-20
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