A memory device includes a cell region in which memory blocks are disposed, each memory block including word lines stacked on a substrate, and channel structures penetrating through the word lines, and a peripheral circuit region including peripheral circuits executing an erase operation of deleting data for each of the memory blocks as a unit. The peripheral circuits control a voltage applied to each word line included in a target memory block to delete data in the erase operation, based on at least one of a position of the target memory block, a height of each word line included in the target memory block, and a profile of each channel structure.