Invention Grant
- Patent Title: Chip packaging method and chip packaging structure
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Application No.: US17598270Application Date: 2020-09-25
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Publication No.: US11552028B2Publication Date: 2023-01-10
- Inventor: Linping Li , Jinghao Sheng , Zhou Jiang
- Applicant: HUZHOU JIANWENLU TECHNOLOGY CO., LTD.
- Applicant Address: CN Huzhou
- Assignee: HUZHOU JIANWENLU TECHNOLOGY CO., LTD.
- Current Assignee: HUZHOU JIANWENLU TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Huzhou
- Agency: Kilpatrick Townsend & Stockton, LLP
- Priority: CN201910978107.6 20191015
- International Application: PCT/CN2020/117655 WO 20200925
- International Announcement: WO2021/073401 WO 20210422
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/552 ; H01L21/48 ; H01L21/78 ; H01L23/498 ; H01L23/00
Abstract:
A method for packaging a chip and a chip packaging structure. A passivation layer is provided on bonding pads of a wafer, a first metal bonding layer is formed on the passivation layer, and a second metal bonding layer is formed on a substrate. The substrate and the wafer are bonded via the first metal bonding layer and the second metal bonding layer, and are packaged as a whole. A first shielding layer is provided on the substrate, and the first shielding layer is in contact with the second metal bonding layer. After the wafer and the substrate are bonded, the wafer is subject to half-cutting to expose the first metal bonding layer. Then, the second shielding layer electrically connected to the first metal bonding layer is formed.
Public/Granted literature
- US20220181269A1 CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE Public/Granted day:2022-06-09
Information query
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