Invention Grant
- Patent Title: Method of making multiple nano layer transistors to enhance a multiple stack CFET performance
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Application No.: US17381384Application Date: 2021-07-21
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Publication No.: US11552080B2Publication Date: 2023-01-10
- Inventor: H. Jim Fulford , Mark I. Gardner
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/092 ; H01L21/822 ; H01L21/8238 ; H01L21/8258

Abstract:
In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.
Public/Granted literature
- US20210351180A1 METHOD OF MAKING MULTIPLE NANO LAYER TRANSISTORS TO ENHANCE A MULTIPLE STACK CFET PERFORMANCE Public/Granted day:2021-11-11
Information query
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