Invention Grant
- Patent Title: Transmission circuit and transmission system adopting reduced number of interfaces
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Application No.: US17482474Application Date: 2021-09-23
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Publication No.: US11552659B2Publication Date: 2023-01-10
- Inventor: Yan-Guei Chen , Liang-Wei Huang
- Applicant: Realtek Semiconductor Corp.
- Applicant Address: TW HsinChu
- Assignee: Realtek Semiconductor Corp.
- Current Assignee: Realtek Semiconductor Corp.
- Current Assignee Address: TW HsinChu
- Agent Winston Hsu
- Priority: TW109133002 20200924
- Main IPC: H04B1/04
- IPC: H04B1/04 ; H04L1/00 ; H03M9/00 ; H04B1/18

Abstract:
A transmission circuit includes a data input pin, a serial-to-parallel converter, an interface decoder, a parallel-to-serial converter, and a processor circuit. The serial-to-parallel converter is electrically coupled to the data input pin. The serial-to-parallel converter converts a plurality of data signals received by the first data input pin into a set of parallel data signals. The interface decoder is electrically coupled to the serial-to-parallel converter. The interface decoder decodes the set of parallel data signals to generate a set of decoded data signals for parallel transmission. The parallel-to-serial converter is electrically coupled to the interface decoder. The parallel-to-serial converter converts the set of decoded data signals into a plurality of input data signals for serial transmission. The processor circuit is electrically coupled to the parallel-to-serial converter. The processor circuit receives and processes the plurality of input data signals.
Public/Granted literature
- US20220094377A1 TRANSMISSION CIRCUIT AND TRANSMISSION SYSTEM ADOPTING REDUCED NUMBER OF INTERFACES Public/Granted day:2022-03-24
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