Invention Grant
- Patent Title: Enhanced word line stripe erase abort detection
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Application No.: US17357053Application Date: 2021-06-24
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Publication No.: US11557348B1Publication Date: 2023-01-17
- Inventor: Vinayak Bhat , Amiya Banerjee , Shrinidhi Kulkarni
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Rutan & Tucker, LLP
- Agent Ravi Mohan
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G11C16/04 ; G11C16/26 ; G11C16/08 ; G06F3/06 ; G06F11/10

Abstract:
Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.
Public/Granted literature
- US20220415403A1 Enhanced Word Line Stripe Erase Abort Detection Public/Granted day:2022-12-29
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