- Patent Title: Combined ECC and transparent memory test for memory fault detection
-
Application No.: US16542776Application Date: 2019-08-16
-
Publication No.: US11557365B2Publication Date: 2023-01-17
- Inventor: Jan-Peter Schat
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G11C29/52 ; G06F11/10 ; G11C11/4096 ; G11C29/56 ; G11C29/44 ; G11C29/10 ; G11C29/12

Abstract:
Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.
Public/Granted literature
- US20210050068A1 Combined ECC And Transparent Memory Test For Memory Fault Detection Public/Granted day:2021-02-18
Information query