Invention Grant
- Patent Title: Cavity structures in integrated circuit package supports
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Application No.: US16113109Application Date: 2018-08-27
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Publication No.: US11557489B2Publication Date: 2023-01-17
- Inventor: Rahul Jain , Sai Vadlamani , Junnan Zhao , Ji Yong Park , Kyu Oh Lee , Cheng Xu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/00 ; H01L23/495 ; H01L23/31

Abstract:
Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.
Public/Granted literature
- US20200066543A1 CAVITY STRUCTURES IN INTEGRATED CIRCUIT PACKAGE SUPPORTS Public/Granted day:2020-02-27
Information query
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