Invention Grant
- Patent Title: Integrated circuits (IC's) with electro-migration (EM)—resistant segments in an interconnect level
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Application No.: US16649901Application Date: 2017-12-27
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Publication No.: US11557536B2Publication Date: 2023-01-17
- Inventor: Kevin Lin , Christopher J. Jezewski , Manish Chandhok
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- International Application: PCT/US2017/068590 WO 20171227
- International Announcement: WO2019/132899 WO 20190704
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768

Abstract:
Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define a first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in an underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.
Public/Granted literature
- US20200279806A1 INTEGRATED CIRCUITS (IC's) WITH ELECTRO-MIGRATION (EM) - RESISTANCE SEGMENTS IN AN INTERCONNECT LEVEL Public/Granted day:2020-09-03
Information query
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