Invention Grant
- Patent Title: 3D trench reference planes for integrated-circuit die packages
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Application No.: US16818603Application Date: 2020-03-13
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Publication No.: US11557552B2Publication Date: 2023-01-17
- Inventor: Chin Lee Kuan , Jackson Chung Peng Kong , Bok Eng Cheah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Priority: MYPI2019003326 20190612
- Main IPC: H01L23/66
- IPC: H01L23/66 ; H01L23/498
Abstract:
A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.
Information query
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