Invention Grant
- Patent Title: High density 3D layout enhancement of multiple CMOS devices
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Application No.: US17237609Application Date: 2021-04-22
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Publication No.: US11557657B2Publication Date: 2023-01-17
- Inventor: H. Jim Fulford , Mark I. Gardner
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8234 ; H01L27/06 ; H01L21/8238 ; H01L29/786 ; H01L29/66 ; H01L29/78 ; H01L27/088 ; H01L21/822

Abstract:
Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include forming a multilayer stack on a substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming at least one opening through the multilayer stack to uncover the substrate and forming at least two vertical channel structures within the opening that are stacked on each other. The vertical channel structures can have source, gate and drain regions being in contact with the metal layers of the multilayer stack, respectively. The method can also include removing a central portion of the vertical channel structures and filling the central portion of the vertical channel structures with a dielectric core. The dielectric core can isolate the vertical channel structures from each other and from the substrate.
Public/Granted literature
- US20220140112A1 HIGH DENSITY 3D LAYOUT ENHANCEMENT OF MULTIPLE CMOS DEVICES Public/Granted day:2022-05-05
Information query
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