- Patent Title: Semiconductor device having trench gate electrodes formed in first pillars including source layers formed in the first pillars being deeper into the substrate than first source layers in second pillars
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Application No.: US17269254Application Date: 2018-10-25
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Publication No.: US11557671B2Publication Date: 2023-01-17
- Inventor: Masanao Ito , Masayuki Furuhashi
- Applicant: Mitsubishi Electric Corporation
- Applicant Address: JP Tokyo
- Assignee: Mitsubishi Electric Corporation
- Current Assignee: Mitsubishi Electric Corporation
- Current Assignee Address: JP Tokyo
- Agency: Xsensus LLP
- International Application: PCT/JP2018/039701 WO 20181025
- International Announcement: WO2020/084736 WO 20200430
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/16 ; H01L29/66 ; H02M3/158
Abstract:
A semiconductor device of the present invention includes a semiconductor region having a first main surface, wherein the semiconductor region includes: alternating n-type pillar layers and p-type pillar layers along the first main surface; a p-type first well layer located within each of the n-type pillar layers at a top surface of the n-type pillar layer; an n-type first source layer located within the first well layer at a top surface of the first well layer; a first side surface dielectric layer located on a side surface in a first trench located at each of boundaries between the n-type pillar layers and the p-type pillar layers, and being in contact with the first well layer and the first source layer; a first bottom surface dielectric layer located on a bottom surface in the first trench, and being at least partially in contact with one of the p-type pillar layers.
Public/Granted literature
- US20210167204A1 SEMICONDUCTOR DEVICE AND POWER CONVERTER Public/Granted day:2021-06-03
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