Invention Grant
- Patent Title: Efficient inter-chip interconnect topology for distributed parallel deep learning
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Application No.: US16777683Application Date: 2020-01-30
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Publication No.: US11561840B2Publication Date: 2023-01-24
- Inventor: Liang Han , Yang Jiao
- Applicant: ALIBABA GROUP HOLDING LIMITED
- Applicant Address: KY Grand Cayman
- Assignee: ALIBABA GROUP HOLDING LIMITED
- Current Assignee: ALIBABA GROUP HOLDING LIMITED
- Current Assignee Address: KY Grand Cayman
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06N3/063 ; G06N3/08
Abstract:
The present disclosure provides a system comprising: a first group of computing nodes and a second group of computing nodes, wherein the first and second groups are neighboring devices and each of the first and second groups comprising: a set of computing nodes A-D, and a set of intra-group interconnects, wherein the set of intra-group interconnects communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C; and a set of inter-group interconnects, wherein the set of inter-group interconnects communicatively couple computing node A of the first group with computing node A of the second group, computing node B of the first group with computing node B of the second group, computing node C of the first group with computing node C of the second group, and computing node D of the first group with computing node D of the second group.
Public/Granted literature
- US20210240532A1 EFFICIENT INTER-CHIP INTERCONNECT TOPOLOGY FOR DISTRIBUTED PARALLEL DEEP LEARNING Public/Granted day:2021-08-05
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