The semiconductor device 1 comprises a processor 2, a memory connected to the processor and a control circuit, and comprises an active operation mode and a standby operation mode. The memory comprises a normal mode and a RS mode lower power consumption than the normal mode. The memory comprises SRAMs 7_0 to 7_5 which includes a mode terminal RS_T supplied with mode instruction signals RS1_0 to RS1_5 specifying the normal mode or the RS mode, respectively. The control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_0 to 7_2 in transition period which the semiconductor device transitions from the standby operation mode to the active operation mode. And the control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_3 to 7_5 after transition to the active operation mode.