Invention Grant
- Patent Title: Semiconductor arrangement including a first electrical insulator layer and a second electrical insulator layer and method of making
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Application No.: US16866612Application Date: 2020-05-05
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Publication No.: US11562923B2Publication Date: 2023-01-24
- Inventor: Wei-Liang Chen , Cheng-Hsien Chen , Yu-Lung Yeh , Chuang Chihchous , Yen-Hsiu Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsin-Chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/3065 ; H01L21/311 ; H01L21/8234 ; H01L29/08 ; H01L27/088 ; H01L29/10 ; H01L21/02
Abstract:
A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.
Public/Granted literature
- US20210351067A1 SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING Public/Granted day:2021-11-11
Information query
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