Invention Grant
- Patent Title: Spacer with pattern layout for dual side cooling power module
-
Application No.: US17136286Application Date: 2020-12-29
-
Publication No.: US11562938B2Publication Date: 2023-01-24
- Inventor: Yong Liu , Liangbiao Chen , Yusheng Lin , Chee Hiong Chew
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L21/48 ; H01L23/373 ; H01L23/31 ; H01L23/00

Abstract:
A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.
Public/Granted literature
- US20220208635A1 SPACER WITH PATTERN LAYOUT FOR DUAL SIDE COOLING POWER MODULE Public/Granted day:2022-06-30
Information query
IPC分类: