A MOS IC includes a first circuit including a first plurality of nMOS devices, a first p-tap cell, and a first dummy nMOS cell, and a second circuit including a first plurality of pMOS devices, a first dummy pMOS cell, and a first n-tap cell. The nMOS/pMOS devices are spaced apart in a first direction. The first p-tap cell and the first dummy nMOS cell are adjacent to each other in the first direction between the nMOS devices. The first dummy pMOS cell and the first n-tap cell are adjacent to each other in the first direction between the pMOS devices. The pMOS devices are adjacent to the nMOS devices in a second direction orthogonal to the first direction. The first p-tap cell/the first dummy pMOS cell and the first dummy nMOS cell/the first n-tap cell are respectively adjacent to each other in the second direction.