Invention Grant
- Patent Title: Structure and method for an MRAM device with a multi-layer top electrode
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Application No.: US16510296Application Date: 2019-07-12
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Publication No.: US11563167B2Publication Date: 2023-01-24
- Inventor: Wei-Hao Liao , Hsi-Wen Tien , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L43/02
- IPC: H01L43/02 ; H01L43/12 ; G11C11/16 ; H01L27/22
Abstract:
A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.
Public/Granted literature
- US20200098978A1 Structure and Method for an MRAM Device with a Multi-Layer Top Electrode Public/Granted day:2020-03-26
Information query
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