Invention Grant
- Patent Title: Semiconductor device for detecting failure in address decoder
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Application No.: US17158301Application Date: 2021-01-26
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Publication No.: US11568908B2Publication Date: 2023-01-31
- Inventor: Shunya Nagata , Yoshikazu Saito , Takeshi Hashizume
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2020-016356 20200203
- Main IPC: G11C8/10
- IPC: G11C8/10 ; G11C7/06 ; G11C7/18 ; G11C8/08

Abstract:
A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.
Public/Granted literature
- US20210241808A1 SEMICONDUCTOR DEVICE Public/Granted day:2021-08-05
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