A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines. The memory device also includes a peripheral circuit configured to perform a plurality of program loops to program memory cells, among the plurality of memory cells, connected to a selected word line among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit to set a step voltage based on the number of turned off memory cells among the selected memory cells and then apply a program voltage, to which the step voltage is added, to the selected word line in a next program loop, during a verify operation of a program operation and the verify operation included in each of the plurality of program loops.