Invention Grant
- Patent Title: Electrical overlay measurement methods and structures for wafer-to-wafer bonding
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Application No.: US17194636Application Date: 2021-03-08
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Publication No.: US11569139B2Publication Date: 2023-01-31
- Inventor: Ikue Yokomizo , Michiaki Sano , Kazuto Watanabe , Hajime Yamamoto , Takashi Yamaha , Koichi Ito , Katsuya Kato , Ryo Hiramatsu , Hiroshi Sasaki , Akihiro Tobioka , Liang Li
- Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/528 ; H01L21/66 ; H01L23/00
Abstract:
A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.
Public/Granted literature
- US20220285234A1 ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDING Public/Granted day:2022-09-08
Information query
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