Invention Grant
- Patent Title: Stacked transistors with different gate lengths in different device strata
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Application No.: US16290544Application Date: 2019-03-01
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Publication No.: US11573798B2Publication Date: 2023-02-07
- Inventor: Aaron D. Lilak , Gilbert W. Dewey , Willy Rachmady , Rishabh Mehandru , Ehren Mannebach , Cheng-Ying Huang , Anh Phan , Patrick Morrow
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L29/772
- IPC: H01L29/772 ; G06F9/30 ; G06F9/34 ; H01L29/78 ; H01L29/66 ; H01L29/786 ; H01L29/775
Abstract:
Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.
Public/Granted literature
- US20190196830A1 STACKED TRANSISTORS WITH DIFFERENT GATE LENGTHS IN DIFFERENT DEVICE STRATA Public/Granted day:2019-06-27
Information query
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