Invention Grant
- Patent Title: State determination apparatus, state determination method, and integrated circuit
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Application No.: US15498006Application Date: 2017-04-26
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Publication No.: US11574221B2Publication Date: 2023-02-07
- Inventor: Norikazu Ikoma , Hiromu Hasegawa
- Applicant: MegaChips Corporation , Kyushu Institute of Technology
- Applicant Address: JP Osaka; JP Kitakyushu
- Assignee: MegaChips Corporation,Kyushu Institute of Technology
- Current Assignee: MegaChips Corporation,Kyushu Institute of Technology
- Current Assignee Address: JP Osaka; JP Kitakyushu
- Agency: Xsensus LLP
- Priority: JPJP2016-089034 20160427
- Main IPC: G06N7/00
- IPC: G06N7/00 ; G06N20/00

Abstract:
Provided is a state determination apparatus that appropriately performs pattern classification processing and/or pattern determination processing even when a map generated by the SOM technique includes discontinuous image regions. In the state determination apparatus, the matching processing unit obtains adaptability data indicating a correlation degree between template data indicating a state and the SOM output data. The state determination unit obtains a state evaluation value based on an activity value obtained by the activity value obtaining unit and the adaptability value. The time series estimation unit determines a state of an input data based on the state evaluation value and state transition probability between states. This allows for appropriately performing pattern classification processing and/or pattern determination processing even when a map generated by the SOM technique includes discontinuous image regions.
Public/Granted literature
- US20170316332A1 STATE DETERMINATION APPARATUS, STATE DETERMINATION METHOD, AND INTEGRATED CIRCUIT Public/Granted day:2017-11-02
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06N | 基于特定计算模型的计算机系统 |
G06N7/00 | 基于特定数学模式的计算机系统 |