Invention Grant
- Patent Title: Data latch circuit and semiconductor memory device
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Application No.: US17109853Application Date: 2020-12-02
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Publication No.: US11574663B2Publication Date: 2023-02-07
- Inventor: Keisuke Nakatsuka , Tomoya Sanuki , Takashi Maeda , Go Shikata , Hideaki Aochi
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JPJP2018-172343 20180914,JPJP2019-044614 20190312
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/08 ; H01L27/11573 ; G11C16/26 ; H01L27/11529 ; G11C7/18
Abstract:
A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
Public/Granted literature
- US20210090616A1 DATA LATCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2021-03-25
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