Invention Grant
- Patent Title: Seal ring between interconnected chips mounted on an integrated circuit
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Application No.: US17385939Application Date: 2021-07-27
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Publication No.: US11574847B2Publication Date: 2023-02-07
- Inventor: Hsien-Wei Chen , Jie Chen , Ming-Fa Chen , Chih-Chia Hu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/48 ; H01L21/00 ; H01L23/10 ; H01L23/31 ; H01L23/538 ; H01L25/065 ; H01L23/522
Abstract:
A forming method of a semiconductor package includes the following steps. A first die is provided. The first die includes a first bonding structure and a first seal ring, the first bonding structure is formed at a first side of the first die, a first portion of the first seal ring is formed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. A second die is provided. The second die includes a second bonding structure. The first die and the second die are bonded onto an integrated circuit through the first bonding structure and the second bonding structure.
Public/Granted literature
- US20210358821A1 METHODS OF FORMING SEMICONDUCTOR PACKAGES WITH SHORTENED TALKING PATH Public/Granted day:2021-11-18
Information query
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