Invention Grant
- Patent Title: Method for fabricating semiconductor device including capacitor structure
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Application No.: US17380603Application Date: 2021-07-20
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Publication No.: US11574914B2Publication Date: 2023-02-07
- Inventor: Jar-Ming Ho
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L23/52 ; H01L23/522

Abstract:
The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts.
Public/Granted literature
- US20210351190A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2021-11-11
Information query
IPC分类: