Invention Grant
- Patent Title: Method for manufacturing semiconductor device including step of simultaneous formation of plurality of contact openings
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Application No.: US17315600Application Date: 2021-05-10
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Publication No.: US11574944B2Publication Date: 2023-02-07
- Inventor: Motomu Kurata , Ryota Hodo , Yuta Iida
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Husch Blackwell LLP
- Priority: JPJP2015-069654 20150330
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L27/146 ; H01L27/12 ; H01L29/423 ; H01L29/49 ; H01L29/66 ; H01L29/786 ; H01L21/8258 ; H01L23/00 ; H01L27/06 ; H01L27/1156

Abstract:
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.
Public/Granted literature
- US20210327937A1 Method for Manufacturing Semiconductor Device Public/Granted day:2021-10-21
Information query
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