Invention Grant
- Patent Title: Forming gate last vertical FET with self-aligned spacers and junctions
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Application No.: US17324894Application Date: 2021-05-19
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Publication No.: US11575024B2Publication Date: 2023-02-07
- Inventor: Nicolas Loubet
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Samuel Waldbaum
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/225 ; H01L29/16 ; H01L21/308

Abstract:
Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.
Public/Granted literature
- US20210328045A1 Forming Gate Last Vertical FET With Self-Aligned Spacers and Junctions Public/Granted day:2021-10-21
Information query
IPC分类: