Invention Grant
- Patent Title: Dummy dielectric fin design for parasitic capacitance reduction
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Application No.: US17222608Application Date: 2021-04-05
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Publication No.: US11575027B2Publication Date: 2023-02-07
- Inventor: Kuo-Cheng Ching , Chih-Hao Wang , Shi Ning Ju , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/092 ; H01L29/417 ; H01L29/51 ; H01L29/78 ; H01L21/8234 ; H01L27/088 ; H01L21/8238 ; H01L29/06 ; H01L29/08

Abstract:
A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.
Public/Granted literature
- US20210226037A1 Dummy Dielectric Fin Design for Parasitic Capacitance Reduction Public/Granted day:2021-07-22
Information query
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