Invention Grant
- Patent Title: Transistor arrangement with a load transistor and a sense transistor
-
Application No.: US17104216Application Date: 2020-11-25
-
Publication No.: US11575041B2Publication Date: 2023-02-07
- Inventor: Gerhard Noebauer
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Priority: EP18151843 20180116
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/40 ; H01L29/06 ; H01L29/08 ; G01R19/00

Abstract:
A method of current detection includes providing a transistor arrangement which comprises a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each having a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each having a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor; and detecting a first current flowing between the drain node and the first source node of the transistor arrangement, wherein detecting the first current includes measuring a second current flowing between the drain node and the second source node of the transistor arrangement.
Public/Granted literature
- US20210083104A1 Transistor Arrangement with a Load Transistor and a Sense Transistor Public/Granted day:2021-03-18
Information query
IPC分类: