Invention Grant
- Patent Title: Fast and scalable methodology for analog defect detectability analysis
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Application No.: US17232009Application Date: 2021-04-15
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Publication No.: US11579994B2Publication Date: 2023-02-14
- Inventor: Mayukh Bhattacharya , Huiping Huang , Antony Fan
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Andrew L. Dunlap
- Main IPC: G06F11/263
- IPC: G06F11/263

Abstract:
A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.
Public/Granted literature
- US20210326227A1 FAST AND SCALABLE METHODOLOGY FOR ANALOG DEFECT DETECTABILITY ANALYSIS Public/Granted day:2021-10-21
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