Invention Grant
- Patent Title: Sub-sense amplifier layout scheme to reduce area
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Application No.: US17342565Application Date: 2021-06-09
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Publication No.: US11581033B2Publication Date: 2023-02-14
- Inventor: Hisayuki Nagamine
- Applicant: Powerchip Semiconductor Manufacturing Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: G11C7/06
- IPC: G11C7/06 ; G11C11/4091 ; G11C11/408 ; G11C7/10 ; G11C11/22

Abstract:
A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.
Public/Granted literature
- US20220399051A1 SUB-SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2022-12-15
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