Invention Grant
- Patent Title: Iterative read calibration enhanced according to patterns of shifts in read voltages
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Application No.: US17485093Application Date: 2021-09-24
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Publication No.: US11581047B2Publication Date: 2023-02-14
- Inventor: James Fitzpatrick , Sivagnanam Parthasarathy , Patrick Robert Khayat , AbdelHakim S. Alhussien
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C16/26 ; G11C16/10 ; G11C11/56 ; G11C29/50

Abstract:
A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts.
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