Invention Grant
- Patent Title: Fill pattern to enhance ebeam process margin
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Application No.: US17388945Application Date: 2021-07-29
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Publication No.: US11581162B2Publication Date: 2023-02-14
- Inventor: Shakul Tandon , Mark C. Phillips , Shem O. Ogadhoh , John A. Swanson
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01J37/30
- IPC: H01J37/30 ; H01J37/317 ; H01L21/027 ; H01J37/04 ; H01L21/033

Abstract:
Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.
Public/Granted literature
- US20210358713A1 FILL PATTERN TO ENHANCE EBEAM PROCESS MARGIN Public/Granted day:2021-11-18
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