Invention Grant
- Patent Title: Sector cache for compression
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Application No.: US17191473Application Date: 2021-03-03
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Publication No.: US11586548B2Publication Date: 2023-02-21
- Inventor: Abhishek R. Appu , Altug Koker , Joydeep Ray , David Puffer , Prasoonkumar Surti , Lakshminarayanan Striramassarma , Vasanth Ranganathan , Kiran C. Veernapu , Balaji Vembu , Pattabhiraman K
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F12/0877
- IPC: G06F12/0877 ; G06F12/0802 ; G06F12/0855 ; G06F12/0806 ; G06F12/0846 ; G06F12/0868 ; G06T1/60 ; G06F12/126 ; G06F12/0893

Abstract:
In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20210191872A1 SECTOR CACHE FOR COMPRESSION Public/Granted day:2021-06-24
Information query
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