Invention Grant
- Patent Title: Thermal bump networks for integrated circuit device assemblies
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Application No.: US16219158Application Date: 2018-12-13
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Publication No.: US11587843B2Publication Date: 2023-02-21
- Inventor: Prasad Ramanathan , Nicholas Neal , Chandra Mohan Jha
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/52 ; H01L23/367 ; H01L23/498 ; H01L23/522 ; H01L23/538 ; H01L23/00 ; H01L23/373

Abstract:
Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.
Information query
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