Invention Grant
- Patent Title: Stacked semiconductor structure and method
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Application No.: US17223292Application Date: 2021-04-06
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Publication No.: US11587910B2Publication Date: 2023-02-21
- Inventor: Szu-Ying Chen , Meng-Hsun Wan , Dun-Nian Yaung
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/00

Abstract:
A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.
Public/Granted literature
- US20210225813A1 Stacked Semiconductor Structure and Method Public/Granted day:2021-07-22
Information query
IPC分类: