Invention Grant
- Patent Title: Multichip package manufacturing process
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Application No.: US17034221Application Date: 2020-09-28
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Publication No.: US11587923B2Publication Date: 2023-02-21
- Inventor: Po-Chuan Lin
- Applicant: eGalax_eMPIA Technology Inc.
- Applicant Address: TW Taipei
- Assignee: eGalax_eMPIA Technology Inc.
- Current Assignee: eGalax_eMPIA Technology Inc.
- Current Assignee Address: TW Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: TW109125166 20200724
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L25/07 ; H01L23/00 ; H01L23/498 ; H01L21/78 ; H01L21/66 ; H01L21/48 ; H01L23/495

Abstract:
Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.
Public/Granted literature
- US20220028851A1 MULTICHIP PACKAGE MANUFACTURING PROCESS Public/Granted day:2022-01-27
Information query
IPC分类: