An array substrate includes a gate layer, a first insulating layer, a channel layer, a source-drain layer, a second insulating layer, and a common electrode layer that are sequentially stacked, wherein the second insulating lay is provided with via holes formed therein; and the source-drain layer includes a plurality of sources, a plurality of drains, a plurality of data lines and a plurality of common electrode signal lines. The common electrode signal line includes a plurality of common electrode signal line segments, each of the common electrode signal line segments passes through at least one sub-pixel row, and each of the common electrode signal line segments is connected to the common electrode layer through the via hole.