Invention Grant
- Patent Title: Sharing instruction cache lines between multiple threads
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Application No.: US17341209Application Date: 2021-06-07
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Publication No.: US11593109B2Publication Date: 2023-02-28
- Inventor: Sheldon Bernard Levenstein , Nicholas R. Orzol , Christian Gerhard Zoellin , David Campbell
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Intelletek Law Group, PLLC
- Agent Gabriel Daniel, Esq.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F12/0875 ; G06F9/32

Abstract:
Aspects are provided for sharing instruction cache footprint between multiple threads using instruction cache set/way pointers and a tracking table. The tracking table is built up over time for shared pages, even when the instruction cache has no access to real addresses or translation information. A set/way pointer to an instruction cache line is derived from the system memory address associated with a first thread's instruction fetch. The set/way pointer is stored as a surrogate for the system memory address in both an instruction cache directory (IDIR) and a tracking table. Another set/way pointer to an instruction cache line is derived from the system memory address associated with a second thread's instruction fetch. A match is detected between the set/way pointer and the other set/way pointer. The instruction cache directory is updated to indicate that the instruction cache line is shared between multiple threads.
Public/Granted literature
- US20220391208A1 SHARING INSTRUCTION CACHE LINES BETWEEN MULITPLE THREADS Public/Granted day:2022-12-08
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