Invention Grant
- Patent Title: Forming method of capacitor array and semiconductor structure
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Application No.: US17648144Application Date: 2022-01-17
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Publication No.: US11594423B2Publication Date: 2023-02-28
- Inventor: Qiang Wan
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Cooper Legal Group, LLC
- Priority: CN202110772178.8 20210708
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L27/01 ; H01L21/3105

Abstract:
The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.
Public/Granted literature
- US20230012790A1 FORMING METHOD OF CAPACITOR ARRAY AND SEMICONDUCTOR STRUCTURE Public/Granted day:2023-01-19
Information query
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