Invention Grant
- Patent Title: Semiconductor device structure with multiple liners and method for forming the same
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Application No.: US17245795Application Date: 2021-04-30
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Publication No.: US11594447B2Publication Date: 2023-02-28
- Inventor: Chia-Hsiang Hsu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L27/06 ; H01L27/1159

Abstract:
A semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer disposed over the semiconductor substrate, and a silicon layer disposed over the buried oxide layer. The semiconductor device structure also includes a first shallow trench isolation (STI) structure penetrating through the silicon layer and the buried oxide layer and extending into the semiconductor substrate. The first STI structure includes a first liner contacting the semiconductor substrate and the silicon layer, a second liner covering the first liner and contacting the buried oxide layer, and a third liner covering the second liner. The first liner, the second liner and the third liner are made of different materials. The first STI structure also includes a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.
Public/Granted literature
- US20220352008A1 SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE LINERS AND METHOD FOR FORMING THE SAME Public/Granted day:2022-11-03
Information query
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