Invention Grant
- Patent Title: Method of forming a device with split gate non-volatile memory cells, HV devices having planar channel regions and FINFET logic devices
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Application No.: US17716950Application Date: 2022-04-08
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Publication No.: US11594453B2Publication Date: 2023-02-28
- Inventor: Serguei Jourba , Catherine Decobert , Feng Zhou , Jinho Kim , Xian Liu , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L21/77
- IPC: H01L21/77 ; H01L27/11517 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/788

Abstract:
A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
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