Invention Grant
- Patent Title: Plurality of leads between MOSFET chips
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Application No.: US17201544Application Date: 2021-03-15
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Publication No.: US11594476B2Publication Date: 2023-02-28
- Inventor: Tatsuya Ohguro , Hideharu Kojima
- Applicant: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- Applicant Address: JP Tokyo; JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee Address: JP Tokyo; JP Tokyo
- Agency: Allen & Overy LLP
- Priority: JPJP2020-154924 20200915
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/00 ; H01L23/495 ; H01L23/00 ; H01L23/31

Abstract:
A semiconductor device includes: a first chip including first and second electrodes provided at a first surface, and a third electrode provided at a second surface positioned at a side opposite to the first surface; a second chip including fourth and fifth electrodes provided at a third surface, and a sixth electrode provided at a fourth surface positioned at a side opposite to the third surface, wherein the second chip is disposed to cause the third surface to face the first surface; a first connector disposed between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector disposed between the second electrode and the fifth electrode and connected to the second and fifth electrodes.
Public/Granted literature
- US20220084917A1 SEMICONDUCTOR DEVICE Public/Granted day:2022-03-17
Information query
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