Invention Grant
- Patent Title: Stacked chips comprising interconnects
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Application No.: US17183027Application Date: 2021-02-23
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Publication No.: US11594521B2Publication Date: 2023-02-28
- Inventor: Masaru Koyanagi
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: KIOXIA CORPORATION
- Current Assignee: KIOXIA CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JPJP2018-132427 20180712
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/522 ; H01L27/06 ; H01L27/11551 ; H01L27/11578 ; H01L21/768 ; H01L25/065 ; H01L23/00 ; H01L25/10 ; H01L25/07 ; H01L25/11 ; H01L27/24

Abstract:
A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.
Public/Granted literature
- US20210175212A1 SEMICONDUCTOR DEVICE Public/Granted day:2021-06-10
Information query
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