Invention Grant
- Patent Title: Semiconductor substrate and semiconductor arrangement
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Application No.: US16892445Application Date: 2020-06-04
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Publication No.: US11594527B2Publication Date: 2023-02-28
- Inventor: Juergen Esch
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Priority: EP19178600 20190606
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L25/065

Abstract:
A semiconductor substrate includes a dielectric insulation layer and a structured metallization layer having at least five separate sections attached to the dielectric insulation layer, a first switching element having first emitter and collector terminals, a second switching element having second emitter and collector terminals, a first diode element having first anode and cathode terminals, and a second diode element having second anode and cathode terminals. The switching and diode elements are arranged on a first section of the metallization layer, with the collector and cathode terminals electrically coupled to the first section. The first anode and emitter terminals are electrically coupled to second and third sections. The second anode and emitter terminals are electrically coupled to fourth and fifth sections. The first section separates the second and fourth adjacent sections from the third and fifth adjacent sections.
Information query
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