Invention Grant
- Patent Title: Layout modification method for exposure manufacturing process
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Application No.: US17330678Application Date: 2021-05-26
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Publication No.: US11594528B2Publication Date: 2023-02-28
- Inventor: Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; G03F1/36 ; G06F30/30 ; G06F30/39 ; G06F30/20 ; G06F119/18

Abstract:
A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.
Public/Granted literature
- US20210296303A1 LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS Public/Granted day:2021-09-23
Information query
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