Invention Grant
- Patent Title: Method to reduce breakdown failure in a MIM capacitor
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Application No.: US17501269Application Date: 2021-10-14
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Publication No.: US11594593B2Publication Date: 2023-02-28
- Inventor: Hsing-Lien Lin , Chii-Ming Wu , Chia-Shiung Tsai , Chung-Yi Yu , Rei-Lin Chu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/00 ; H01L49/02 ; H01L21/768 ; H01L21/02 ; H01L23/64 ; H01L27/22

Abstract:
Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.
Public/Granted literature
- US20220069068A1 METHOD TO REDUCE BREAKDOWN FAILURE IN A MIM CAPACITOR Public/Granted day:2022-03-03
Information query
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