A controller includes a phase frequency detection circuit which has a first input coupled to receive a reference clock input, a second input coupled to receive a high-side active output, and an output configured to provide a PFD output. The controller includes a control loop filter which has a first input coupled to receive a slew rate input, a second input coupled to receive the PFD output, and an output configured to provide a high-side length output. The controller includes a pulse generation circuit which has a first input coupled to receive the high-side active output, a second input coupled to receive the high-side length output, and an output configured to provide a fine pulse output. The controller includes a latch configured to provide the high-side active output responsive to a comparison output and the fine pulse output.